The present invention relates generally to layered structures, and more particularly to layered structures on thin substrates.
U.S. Pat. No. 7,141,210 describes nanocalorimeter arrays with thermal isolation regions on a substrate. A thermal isolation layer can include a plastic material in thin foil form ranging from less than 15 μm to approximately 25 μm in thickness, possibly as thin as 2 μm and as thick as 500 μm. Thermal equilibrium regions contain resistive thermometers, drop merging electrodes, and insulating layers deposited using standard fabrication techniques, such as lithographic patterning of thin films, microelectronic fabrication techniques (e.g. including sputtering, chemical etching, evaporation), and printed circuit board fabrication techniques. If amorphous silicon thermometer material is deposited, such as at temperatures in the range of 170-250° C., a substrate polymer film should have a high softening temperature. Deposition of vanadium oxide thermometer material can be done at a substantially lower temperature, allowing a substrate polymer with a lower softening point.
U.S. Pat. No. 6,107,117 describes fabrication of thin film transistors (TFTs) in which the active layer is an organic semiconducting material. Organic materials are compatible with plastic substrates on which thin film field effect transistors (FETs) are typically formed. An insulating layer of organic material can be printed on the substrate using a screen mask made of stainless steel fabric. The organic material is applied to the stainless steel fabric and a squeegee is used to press the organic material through the openings in the screen and onto the substrate surface. The active organic semiconducting material is formed by applying a solution of regioregular organic polymer and an appropriate solvent, using conventional techniques such as spin-coating, casting, or printing.
U.S. Pat. No. 6,972,261 describes fabrication of fine features by jet-printing and surface treatment. One specific application is to form a polymeric-semiconductor TFT. A conductive layer is deposited onto a substrate, such as silicon, glass, quartz, or a polymeric-based flexible material. A patterned etch mask layer is printed over the conductive layer, and wet or dry etchant is used to remove the exposed conductive layer. Other layers are similarly deposited and etched with printed mask layers.
U.S. Patent Application Publication 2005/0129843 describes a nanoparticle deposition process that includes solution depositing a composition on a substrate and heating the depositing composition. Examples of “solution depositing” include solution coating and solution printing. Illustrative solution printing techniques include, for example, screen printing, stencil printing, inkjet printing, stamping (such as microcontact printing), and the like. The substrate may be composed of silicon wafer, glass plate, metal sheet, plastic film or sheet. For structurally flexible devices, plastic substrate, such as polyester, polycarbonate, polyimide sheets and the like may be used. The thickness may be from about 10 micrometers to over 10 millimeters with an exemplary thickness being from about 50 micrometers to about 2 millimeters, especially for a flexible plastic substrate, and from about 0.4 to about 10 millimeters for a rigid substrate such as glass or silicon.
It would be advantageous to have improved techniques for layered structures on thin substrates.